Technical Specifications
Deep dive into the architecture, instruction set, and physical implementation.
bpcore-silicon-docs ~ architecture
NeuraEdge™ Architecture
Tile-Based Scalability
The NeuraEdge NPU is built on a modular tile-based architecture connected by a high-bandwidth 2D mesh network.
›Compute Tile: Each tile contains a RISC-V controller and a systolic array for Int8 matrix multiplication.
›Mesh Interconnect: A low-latency XY-routing mesh connects tiles, enabling linear performance scaling.
›Distributed Memory: SRAM is distributed across tiles to maximize data locality and minimize off-chip access.
Key Features
›Int8 Quantization: Native support for Int8 inference with Int32 accumulation.
›Sparsity Awareness: Hardware support for skipping zero-valued activations, boosting efficiency.
›DVFS Support: Dynamic Voltage and Frequency Scaling hooks for power optimization.