Own your architecture.
Zero royalties. Forever.
NeuraEdge NPU IP. 256 INT8 MACs. 7-stage ONNX compiler. Full unencrypted RTL — 91 source files, zero black boxes. Architected for TSMC 28nm migration. One-time acquisition. Zero royalties. Forever.
238 verified delivery files. SHA-256 manifest. Cadence/Synopsys-ready RTL.
INT8 MACs
2×2 mesh · 4×4 PE per tile
Tests Passing
96% functional coverage
DRC Violations
LVS clean · Netgen verified
Delivery Files
SHA-256 verified package
What we build
Production-ready NPU IP cores with a zero-royalty buyout model. We bypass the complex licensing of legacy vendors: you buy it once, and you own the IP outright. By delivering 100% readable, modifiable, and auditable RTL to drop straight into your design flow, we drastically cut your time-to-market and eliminate the R&D risk of silicon failure. Because you hold the source code, you can fully white-label the architecture, transforming it from a rented tool into a permanent proprietary asset on your balance sheet that directly increases your company's valuation. Included: 7-stage ONNX-to-binary compiler (14 operators, ResNet-18 verified end-to-end). RTL architected for commercial node migration — TSMC 28nm roadmap available under NDA.
Who we serve
Fabless semiconductor companies building custom SoCs for edge inference. Whether your silicon targets defense systems, industrial vision, or medical devices, we built this for you. We serve teams who want to own their technology stack from the RTL up, bypassing foreign middlemen to build truly independent hardware.
What to expect
Direct, architect-to-architect transparency. We bypass the traditional sales layer entirely. When you have a question, you get an answer directly from the architects who built the block. We deliver complete, unencrypted source files because we believe in our architecture. Every metric we claim is verifiable in your own environment. No hidden clauses. No black boxes. Just pure, tape-out-ready RTL.
Driving India's Semiconductor Sovereignty
For decades, Indian engineering talent has designed chips for the world, while Indian companies have been forced to rent critical IP from foreign vendors. We are changing that. By delivering production-ready, royalty-free NPU IP built specifically for the domestic fabless ecosystem, we enable Indian companies to finally own their silicon from the RTL up. Total cost of ownership — not a recurring liability. We are accelerating India's transition from a semiconductor consumer to a sovereign semiconductor creator.
THE REAL COST OF BUILDING IN-HOUSE
Building an NPU in-house? Run the numbers.
Minimal viable team · 28 months · before tape-out
First tape-out success rate: 60–70% industry average. If you miss timing: ₹2–3 Cr respin. If your RTL architect quits mid-project: your problem. If the tool license lapses: your problem.
Estimate your true build cost
₹2.9 Cr
estimated total exposure
vs. NeuraEdge: one-time acquisition. Vs. open-source RISC-V NPU cores: no DFT infrastructure, no ONNX compiler, no physical signoff, no integration support — and 12–18 months to reach equivalent maturity.
SIGNOFF DATA · NOT SLIDEWARE
Every claim is traceable to a source file.
The numbers below are derived from RTL source code, EDA tool outputs, and signoff reports — not marketing estimates. Source file and line number available on request post-NDA.
0
DRC Violations
Magic DRC · neuraedge_top_2x2.gds
LVS clean · Netgen verified
9
MCMM Corners · Positive Slack
OpenSTA · tt / ff / ss × setup / hold / power
100 MHz Fmax @ tt_025C (simulation, SKY130A)
249
Tests Passing
Verilator 5.030 · GLS at 3 corners
96% functional coverage · SymbiYosys formal
80
Scan Chains
rtl/dft/dft_top_controller.sv:35
MBIST March-C− · JTAG IEEE 1149.1 · OPCG
238
Files · SHA-256 Verified
00_MANIFEST/SHA256_manifest.txt
GDS 55MB · LEF · DEF · SPEF · Liberty (4 corners)
7
Stage Compiler
sw/compiler/ · 18 Python modules
ONNX → binary · 14 operators · ResNet-18 verified
Full security assessment and vulnerability disclosure: post-NDA.
MATURITY ASSESSMENT
Honest self-assessment. Every score has evidence.
90+ files · lint-clean · 20+ features RTL-verified
249 tests · 96% coverage · GLS at 3 corners
DRC-clean · LVS-clean · 9-corner MCMM STA
80 scan chains · MBIST · JTAG · ATPG not generated
7-stage · 14 ops · ResNet-18 end-to-end verified
TRM 1,780 lines · 4 app notes · 36 NVLP reports
UPF 3.0 · 5 domains · 8 states · 9-corner STA
Overall: 4.1 / 5.0
Pre-Silicon · RTL-Frozen · Physical Signoff Complete (SKY130A)
CHOOSE YOUR PATH
Three paths to an NPU.
Only one makes financial sense.
Build In-House
— Team cost: ₹1.5–3.5 Cr / year
— Timeline: 24–33 months
— Tool licenses: ₹1–3 Cr / year additional
— First tape-out success: 60–70%
— Attrition risk: high
— Open-source alternative: 12–18 months to reach DFT-complete, compiler-verified maturity equivalent to NeuraEdge v1.0
— Total exposure: ₹8–12 Cr
You own the output. If you survive.
License Traditional IP
— Upfront: $200K–500K USD
— Per-chip royalty: 2–5% of ASP forever
— At 1M units: ₹12–40 Cr bleed
— RTL: encrypted black box
— Debug: support ticket queue
— Geopolitical: ITAR exposure
You are renting. They own the leverage.
Acquire NeuraEdge
— Upfront: one-time acquisition fee
— Per-chip royalty: ₹0. Forever.
— RTL: 100% unencrypted · 91 files
— Debug: complete source access
— Attribution: zero — brand it as yours
— IP on balance sheet: asset, not liability
— Geopolitical: 100% Indian · SCOMET-clean
— Node roadmap: TSMC 28nm / GF 22FDX migration architecture included · commercial PDK porting guide available post-NDA
You own it. Modify it. Ship it.
Request Acquisition Details →FOR DEFENCE & AEROSPACE BUYERS
DAP 2026 demands 'Owned by India.'
NeuraEdge delivers it.
The draft Defence Acquisition Procedure 2026 shifts procurement from 'Made in India' to 'Owned by India' — mandating complete domestic ownership of source code, hardware layout, and architecture across the full system lifecycle.
NeuraEdge satisfies every clause: 100% Indian-designed RTL, complete source code transfer, zero foreign export jurisdiction, SCOMET-clean supply chain.
DAP 2026
Owned by India · Self-Assessed
SCOMET
Category 7 · Domestically Immune
TRL 4
iDEX ADITI Eligible
100% IC
Indigenous Content · DAP 2020
ENGINEERING LEADERSHIP
Architecture backed by verifiable signoff data.
Every performance claim on this site traces to an EDA tool output or a source file line number. No projections presented as measurements. When you schedule a review, we open the signoff logs live — not a slide deck.
— Bandhan Patil, Founder & Chief Architect · Mumbai, Maharashtra
NO COMMITMENT REQUIRED
Request the NeuraEdge one-pager.
Fill in your details. Our engineering team will review your request and send the one-pager to your email. No NDA required.
Our team reviews all requests within one business day. Your information is not shared.
Schedule an Architecture Review.
Not a sales call.
30 minutes. You bring your tape-out requirements. We bring the RTL, the STA reports, and the signoff logs. If NeuraEdge doesn't fit your project — we'll tell you in the first 10 minutes.
You describe your target node and inference workload
We walk through the verification data live on screen
If it fits: NDA → full repo access → commercial proposal
Directly with our core engineering team. No SDR. No pre-qualification. No queue.