PRODUCT ROADMAP
Every gap tracked. Every version committed.
NeuraEdge development follows a versioned roadmap. Every known gap is classified, assigned to a release, and tracked publicly. Timeline estimates are conditional on v1.0 acquisition revenue.
VERSIONED COMMITMENTS
v1.0
DELIVEREDCurrent releasev1.1
Q3 2026 COMMITMENTv2.0
COMMERCIAL NODE RELEASETAPE-OUT JOURNEY
10 phases. From RTL to TSMC submission.
Each phase covers a distinct engineering discipline. v1.0 status shows what is complete today. v2.0 commitment shows what will be delivered for commercial node tape-out. Detailed gap tables are provided in the Post-NDA Technical Package.
| Phase | What it covers | v1.0 status | v2.0 commitment |
|---|---|---|---|
| A — RTL | Lint, CDC, RDC, X-prop | Lint: clean | CDC tool report |
| B — Synth | TSMC 40nm synthesis scripts | RTL ready | DC/Genus scripts |
| C — PD | Floorplan, CTS, physical impl | Architecture | ICC2 flow |
| D — PDN | Power distribution, IR drop | UPF: 5 domains | TSMC 40nm PDN |
| E — Formal | Equivalence checking, proofs | Partial | LEC complete |
| F — DFT | ATPG, scan compression | 80 chains | ATPG patterns |
| G — STA | 9-corner MCMM, AOCV, SI | 3 corners clean | PrimeTime 9-corner |
| H — DRC | Physical verification (TSMC decks) | 0 violations | ICV/PVS flow |
| I — Power | PrimePower sign-off | Gate-level done | Voltus/PrimePower |
| J — Submit | TSMC tape-out package | Delivery package | Full submit package |
Critical path: 12 calendar weeks, 3-person PD team
After TSMC NDA and PDK delivery. Full week-by-week engineering schedule provided in Post-NDA Technical Package.
INTEGRATION TIMELINE
From NDA execution to TSMC tape-out submission:
12 calendar weeks (3-person PD team).
Assumptions
— TSMC PDK and NDA: Week 1–2
— SRAM macros compiled: Week 5
— Commercial EDA tools licensed: Week 1
— No major RTL re-spins required
Full week-by-week engineering schedule provided in Post-NDA Technical Package. Timeline assumes an experienced physical design team with existing TSMC flow infrastructure.
KNOWN GAPS TRACKER
Every gap. Classified. Assigned. Tracked.
| Gap | Target Version | Severity |
|---|---|---|
| ATPG patterns not generated | v1.1 | Medium |
| Formal proofs incomplete (BMC counterexamples from FIFO init) | v1.1 | Low |
| SHA-256 manifest not generated | v1.1 | Low |
| Process migration guide not written | v1.1 | Medium |
| CDC tool report not generated | v1.1 | Medium |
| SRAM macro specification sheets not written | v1.1 | Low |
| Commercial tool signoff (Synopsys/Cadence) not performed | v2.0 | Medium |
| No silicon measurement (all data simulation-derived) | v2.0 | High |
| LPDDR4 interface not designed | v2.0 | Medium |
| ISO 26262 assessment not started | v2.0 | Low |
All timeline estimates are conditional on v1.0 acquisition revenue. Items marked [ESTIMATED] are projections, not commitments.
Shape the roadmap.
v1.1 and v2.0 priorities are influenced by acquisition partner requirements. If your tape-out needs a specific feature or node migration timeline, tell us during the architecture review.