What Buyers Get
High‑confidence, integration‑ready NPU IP: everything required to evaluate, validate, integrate, and scale NeuraEdge with deterministic evidence and full architectural freedom.
Package Overview
| Category | Included Assets | Outcome / Value |
|---|---|---|
| RTL Source | Top, tile, PE, router mesh, sparsity primitives, latency injectors | Full auditability & unlimited customization (no black boxes) |
| Verification Harness | Host adapter, deterministic protocol & numeric suites, stress benches | Fast bring‑up (< 1 day) & reproducible correctness |
| Workload Generators | GEMM, 2‑layer MLP, conv tiling pad/stride matrix | Coverage of boundary dims, flow control & compute variety |
| Formal Collateral | Key handshake & routing properties + SBY configs | Early deadlock & protocol safety confidence |
| PPA / Synthesis Collateral | DVFS wrappers, clock gating stubs, integration checklist | Accelerated timing/power exploration & partition planning |
| Artifacts & Telemetry | CSV (cycles, stalls, inflight, seeds, git SHA), watermarks, digest signatures | Evidence trail for internal diligence & regression gating |
| Sparsity Toolkit | Bitmap RLE decoder, adaptive sparsity FSM | Immediate MAC efficiency uplift without redesign |
| Documentation | Workload suite spec, CI usage, timing roadmap, power/area analysis | Clear engineering narrative for signoff reviews |
| Optional Evaluation Pack | Sanitized RTL subset + workload matrix + golden digests | Low‑friction pre‑purchase technical diligence |
| Support Tiers (Optional) | Advisory → design review → co‑design | Right‑sized engagement aligned to roadmap cadence |
Deliverables (Annotated)
- 1RTL Hierarchy – Human‑readable Verilog/SystemVerilog across all functional domains.
- 2Deterministic Suites – Dual‑run protocol & numeric tests producing byte‑identical CSVs.
- 3Stress & Edge Benches – Stall, reset, padding/stride, and sparsity scenarios.
- 4Formal Properties – Routing progress, credit safety, FIFO bounds (extensible set).
- 5Timing & PPA Collateral – Pipeline enable defines, power/area tradeoff documentation.
- 6Telemetry Signals – Watermarks, watchdog, digest markers for tuning & confidence.
- 7Sparsity Components – Plug‑in efficiency without architecture churn.
- 8Advisory (Optional) – Mesh sizing, DVFS partitioning, buffer depth optimization.
Why It Matters
| Need | Pain Without | Provided Relief |
|---|---|---|
| Fast bring‑up | Weeks of ad‑hoc harness scripting | Turn‑key adapter + deterministic suites |
| Confidence | Anecdotal test coverage | Structured artifacts & formal proofs |
| PPA Exploration | Slow iteration on timing/power | Ready pipeline defines & gating stubs |
| Customization | Vendor gating & opaque IP | Full editable source + clear seams |
| Efficiency | Wasted MACs on zeros | Sparsity decode + adaptive skip path |
Evaluation Path (Optional)
Request: sanitized RTL subset, workload matrix, golden digests, timing snapshot.
Run Time
< 2 min
Run
protocol_flow & protocol_microInspect CSV evidence → Proceed
Quick Integration Checklist
- Clone & lock SHA.
- Run protocol + numeric determinism (expect digest MATCH).
- Execute stress (stalls/resets) & sparsity enable toggle.
- Inspect FIFO watermarks; tune depths (start at 4 → adjust if sustained depth‑1).
- Enable pipeline defines for target Fmax (100 MHz validated baseline).
- Partition DVFS domains (mesh vs. PE) if multi‑frequency needed.
- Formal pass (routing progress, credit non‑negative, FIFO bounds).
- Synthesis snapshot & timing margin review.
Support Tiers (Optional)
| Tier | Scope | SLA |
|---|---|---|
| Base | Artifact Q&A (email) | ≤2 business days |
| Enhanced | Integration advisory & design review | 1 business day |
| Premium | Feature co‑design & formal expansion | Same day |
Artifact Structure Reference
| Artifact | Purpose |
|---|---|
| protocol_flow.csv | Flow robustness metrics |
| protocol_micro.csv | Micro‑kernel determinism |
| numeric.csv | Int8→Int32 corner verification |
| *.log | Handshake & digest trace |
| VCD (on fail) | Debug root cause |
| rtl_workload_suite.md | Scope & status mapping |
Differentiators Snapshot
Licensing
One‑time acquisition; zero royalty
Source Depth
Full hierarchy + collateral (no encryption)
Determinism
Byte‑identical dual‑run evidence
Extensibility
Mesh/flit/FIFO/DVFS knobs & sparsity gating
Timing Confidence
100 MHz validated (Sky130) with margin
Power Efficiency
Sparsity + gating + DVFS hooks
Ready to Evaluate?
Email info@bpcore-silicon.com with subject “NeuraEdge Evaluation Request” to receive the optional evaluation pack or initiate full acquisition.
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