NeuraEdge™ NPU
by BPcore Silicon
Production-Ready AI Acceleration IP.
Royalty-Free. Full Source. Made in India.
BPcore Silicon delivers NeuraEdge™, a production-validated neural processing unit IP engineered for rapid integration, power efficiency, and complete technical independence.
- 100 MHz signoff achieved on Sky130 (TT: 137 MHz, FF: 178 MHz)
- Full RTL source with deterministic validation suites
- One-time acquisition, zero royalties, no per-unit fees
- Mesh-scalable architecture (2×2 → N×N) with sparsity-aware execution
- Made in India 🇮🇳 — Strengthening semiconductor sovereignty
System Status
Nightly Regression
Latest run passed with +2.71ns margin on TT corner.
Production Milestone: 100 MHz Validated
Timing signoff achieved on Sky130 technology with 3-stage pipeline architecture (November 2025).
Timing Signoff (Sky130)
| Corner | Frequency | WNS | Margin | Pipeline | Status |
|---|---|---|---|---|---|
| TT (25°C, 1.80V) | 137 MHz | +2.71ns | +37% | 3-stage | Signoff-Ready |
| FF (-40°C, 1.95V) | 178 MHz | +4.37ns | +78% | 3-stage | Signoff-Ready |
Technical Achievement
Production Validation
- Zero synthesis-to-placement degradation
- CI-protected nightly regression
- Power/area overhead: +3.5% area, ~20% power
- Efficiency: 3.0 MHz per mW
Why NeuraEdge™ Wins
Innovation without lock-in. A new standard for IP ownership.
Full Technical Freedom
Complete human-readable RTL source code. No encrypted black boxes. Audit, modify, customize—unlimited.
Zero Royalty Economics
Single upfront acquisition. Unlimited product deployments. No per-unit, per-core, or per-wafer fees. Ever.
Production-Validated
100 MHz signoff on Sky130 with CI protection. Post-placement timing margins. Ready for immediate tapeout.
Reproducible Validation
Deterministic protocol, numeric, and stress suites generating byte-identical evidence. No guesswork.
Integration Velocity
Structured deliverables: turn-key simulation harness, workload generators, DVFS collateral. Bring up in < 1 day.
Scalable & Extensible
Modular 2×2→N×N mesh without redesign. Sparsity primitives, clock gating, DVFS hooks pre-integrated.
Inside NeuraEdge™
Architected for performance, scalability, and ease of integration.
Modular Tile Mesh
Lightweight NoC routers (5-port XY deterministic) connect compute tiles in 2D topology. Parameterized for 1×1 baseline to N×N scaling.
Int8→Int32 Compute
Optimized integer MAC arrays for dense inference kernels (GEMM, MLP, convolution). High TOPS/W, deterministic numeric behavior.
Sparsity-Aware Execution
Bitmap RLE decoder + adaptive FSM skip zero-lanes. 1.5–2.5× efficiency uplift on sparse workloads without architecture churn.
Deterministic Validation
CSV logs (cycles, stalls, inflight, seeds, git SHA), dual-run A/B protocol suite, numeric corner coverage. Reproducible evidence.
DVFS & Clock Gating
Multi-domain clock/reset wrappers, internal gating stubs. 10–20% dynamic power reduction. CDC-safe partition boundaries.
Key Capabilities
Comprehensive feature set designed for modern edge AI workloads.
| Feature | Specification | Benefit |
|---|---|---|
| Mesh Interconnect | 2D Mesh (XY Routing), 32-bit flits | Scalable bandwidth, no central bottleneck |
| Compute Tile | Int8 MAC Array + RISC-V Controller | High efficiency for quantized inference |
| Sparsity Support | Zero-skipping logic (activations) | 2x speedup on sparse models |
| On-Chip Memory | Distributed SRAM (per tile) | Low latency, high locality |
| External Interface | AXI4-Stream / APB | Standard SoC integration |
Why This Matters
See how NeuraEdge™ compares to traditional licensing models.
| Metric | NeuraEdge™ IP | Traditional IP |
|---|---|---|
| Cost Model | One-time Buyout | License + Royalties |
| Source Code | Full RTL Included | Encrypted / Black Box |
| Customization | Full Rights to Modify | Locked / Change Requests |
| Verification | Deterministic Suites Provided | Limited Test Benches |